CMOS or MOS gates (Complementary Metal-Oxide Semiconductor) refer to the use of two types of transistors in the output circuit in a configuration similar to the TTL family totem pole.
What is Complementary Metal-Oxide Semiconductor?
Both n-channel (NMOS) and p-channel (PMOS) MOSFETs (MOS Field Effect transistors) are used together in the same circuit to achieve various advantages over the P-MOS and N-MOS families. This technology is now dominant because it consumes faster and less power than other MOS families.
These advantages are somewhat overshadowed by the high complexity of the IC manufacturing process and the lower integration density. Therefore, it still cannot compete with MOS in applications that require the latest version in LSI.
Like N-MOS and P-MOS, CMOS has an extremely large input resistance (10 * 12Ω), which draws almost no current from the signal source, each input usually represents a 5pF ground load. Due to the input capacitance, the number of inputs that can be processed with a single output is limited.
Therefore, the load factor depends on the maximum allowable propagation delay. Usually, this load factor is 50 (<1 MHz) for low frequencies. Of course, the load factor is reduced for high frequencies.
The CMOS output must charge and discharge the parallel combination of each input capacitance, so that the output switching time increases in proportion to the number of loads driven, each load increases the transmission delay of the circuit spread by 3 ns. Thus, we can conclude that the load factor depends on the maximum allowable propagation delay.
It has to use relatively large load capacitances such as N-MOS and P-MOS, in all cases the switching speed is higher due to the low output resistance. Recall that an N-MOS output should load the load capacitance with a relatively large resistance (100 k Ω).
In the CMOS circuit, the output resistance in the HIGH state is the RON value of the P-MOSFET, which is usually 1 k Ω or less. This allows the charging capacitance to charge faster. The switching speed values depend on the supply voltage used, for example, in the 4000 series NAND gate, the propagation time is 50 ns for VDD = 5 V and 25ns for VDD = 10 V.
As we can see, although VDD is larger, we can work at higher frequencies. Of course, as VDD grows, the power loss increases. A 74HC or 7411CT series NAND gate has an average of around 8 ns TPD when working with VDD = 5V. This speed is comparable to the speed of the 74LS series.
We can see the power distribution as a constant function within the operating range of the frequency of a TTL gate. Instead, it is frequency-dependent in the CMOS gateway.
In the case of DC, the power loss of the DCOS CI will be very low. Unfortunately, PD will always grow in proportion to the frequency of changing the state of the circuits. Every time an output goes from LOW to HIGH, a momentary oscillating load current must be provided to the load capacitance.
This capacitance consists of the input capacities of the combined loads carried out and the output capacitance of the device itself. These short current pins are provided by VDD and can have a normal amplitude of 5 mA and a duration of 20 to 30 ns.
As the switching frequency increases, it will be more than these current increases per second, and the average VDD current consumption will increase. Therefore, at high frequencies, it starts to lose some advantages over other logic families.
As a general rule, a gate will have the same PD as the average 74LS gate at frequencies of about dc 2 to 3 MHz. The situation for CI MSI is more complex than what is stated here, and a logical designer should perform a detailed analysis to determine whether the CMOS has an advantage in terms of power loss at a given operating frequency.
TTL bipolar circuits require only a volt power supply that tolerates a small deviation. The circuits, on the other hand, allow a greater power range from +2 to +6 volts for the HC and AC series and +3 to +15 volts for the 4000 and 74CXX series. However, there are two CMOS series, HCT and ACT are designed to be compatible with TTL circuits and therefore require a +5 volt supply.
When a TTL input is in the L (low) state, it supplies current to the circuit producing the L Signal (typically 0.25 mA for the LS series).
This should be taken into account when feeding other circuit types to TTL gates. Conversely, in a CMOS circuit, there is no input current. The input threshold required in a TTL gate to cause a change in the output is about two diode breaks. However, this threshold is typically about half of a power source with a significant distribution between 1/3 and 2/3 of the power supply.
Compatible with TTLs, HCT and ACT families are designed to have a low entry threshold, similar to TTLs. As we can see, this is because the H (high) output in TTL circuits does not reach +5 volts.
CMOS inputs are sensitive to permanent damage from static electricity during use. Unused inputs must be properly connected to H or La.
Differences Between CMOS and TTL Families
The most important differences between both families;
In the production of integrated circuits, bipolar transistors for TTL and MOSFET transistors for CMOS technology are used.
It requires much less space due to its compact MOSFET transistors. Moreover, due to their high integration densities, large memory, calculator ICs, microprocessors, and VLSI in LSIs outperform bipolar ICs in the field of large-scale integration.
Integrated circuits have lower power consumption than TTLs.
It is slower than TTL at operating speed.
It has higher noise immunity than TTLs.
It has a larger voltage range and a higher load factor than TTLs.
In summary, we can say TTL is designed for high speed. CMOS: designed for low consumption. Currently, among these two families, others have been created that try to achieve the best of both: low consumption and high speed. The ECL logic family is between TTL and CMOS. This family was born to achieve TTL speed and low CMOS consumption but is rarely used.
Advantages of CMOS over TTL
In the field of MSI, it started to grow steadily, primarily at the expense of TTL, where it competes directly.
The production process is simpler than TTL and has a higher integration density, which allows more circuits in a given substrate area and reduces the cost per function. The biggest advantage of CMOS is that they use only a fraction of the power required for the low power TTL series; this is ideal for applications that use the power of a battery or stand on a battery.
The disadvantage is that it is slower than the TTL family, but the new HCMOS high-speed series that came out in 1983 can compete in terms of speed and current usability and lower levels of advanced bipolar series.
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